1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and in particular, to a technology effectively applied to a semiconductor integrated circuit device having a DRAM (dynamic random access memory).
2. Description of the Related Art
The memory cell of a DRAM is arranged at each of the points of intersection of a plurality of word lines and a plurality of bit lines which are arranged in a matrix on the main surface of a semiconductor substrate, and is constituted by one MISFET (metal insulator semiconductor field effect transistor) for selecting a memory cell and one capacitance element (capacitor) for storing information connected in series thereto.
The above-mentioned MISFET for selecting a memory cell is constituted mainly by a gate oxide film, a gate electrode integrally formed with the word line, and a pair of semiconductor regions which constitute a source and a drain. The capacitance element for storing information is arranged on the top of the MISFET for selecting a memory cell and is electrically connected to one of the pair of source and drain. Also, the bit line is also arranged on the top of the MISFET for selecting a memory cell and is electrically connected to the other of the pair of source and drain.
The above-mentioned DRAM having the capacitance element for storing information on the top of the MISFET for selecting a memory cell, that is, having the so-called stacked capacitor structure adopts either a capacitor-over-bit line (COB) structure in which the capacitance element for storing information is arranged over a bit line or a capacitor-under-bit line (CUB) structure in which the capacitance element for storing information is arranged under the bit line, and the former structure (COB structure) is more suitable for making a finely patterned memory cell. This is because of the following reason; in order to increase the amount of stored charges of the finely patterned capacitance element for storing information, the capacitance element for storing information is required to have a three-dimensional structure to increase its surface area and in the case of the CUB structure in which the bit line is arranged over the capacitance element for storing information, the aspect ratio of a contact hole for connecting the bit line to the MISFET for selecting a memory cell is made extremely large and hence it is difficult to make the contact hole.